// `include "top_define.v"
module look_addr_table_mux(
               input clk  ,
			   input rst_n,

               input looking,
               input looking1,
               input initing,
               //总线1 查找、更新
               input [9:0]   look_addr,
               input [71:0]  look_data,
               input         look_wren,
               //总线1 删除
               input [9:0]   delete_addr,
               input [71:0]  delete_data,
               input         delete_wren,
               //
               input look_update,
			   input [82:0]bus2_fifo_data,
               input [82:0]bus3_fifo_data,
               input [82:0]bus4_fifo_data,
               output reg         q_al_en,              
               output reg [71:0]  bus1_lookup_q,
			   output reg [71:0]  bus2_lookup_q,
			   output reg [71:0]  bus3_lookup_q,
			   output reg [71:0]  bus4_lookup_q,
  
               output reg [9:0] bus1_table_addr,
               output reg       bus1_table_wren,
               output reg [71:0]bus1_table_data,
			   
			   output reg [9:0] bus2_table_addr,
               output reg       bus2_table_wren,
               output reg [71:0]bus2_table_data,
               
               output reg [9:0] bus3_table_addr,
               output reg       bus3_table_wren,
               output reg [71:0]bus3_table_data,
               
               output reg [9:0]  bus4_table_addr,
               output reg        bus4_table_wren,
               output reg [71:0] bus4_table_data,

			   input [71:0] bus1_table_q,
			   input [71:0] bus2_table_q,
			   input [71:0] bus3_table_q,
               input [71:0] bus4_table_q
                     );
reg looking_ff1;
reg looking_ff2;
//总线1查找、更新
always @(*)
begin
	if(looking || initing) begin
	    bus1_table_addr  = look_addr;
		bus1_table_wren  = look_wren;
		bus1_table_data  = look_data;
	end
	else if(!looking) begin//总线1删除
	    bus1_table_addr  = delete_addr;
		bus1_table_wren  = delete_wren;
		bus1_table_data  = delete_data;
	end
	else begin
	    bus1_table_addr  = 10'd0;
		bus1_table_wren  = 1'd0;
		bus1_table_data  = 72'd0;
	end
end
//////////////////////////////////////////////
//总线234的组合逻辑选择结束后还可以打一拍
//待上板验证结束后在进行核对
//////////////////////////////////////////////
//总线2查找
always @(*)
begin
	if(looking1 || initing) begin
	    bus2_table_addr  = look_addr;
		bus2_table_wren  = look_wren;
		bus2_table_data  = look_data;
	end
	else if(/*~looking1*/ look_update) begin//总线2更新、删除
	    bus2_table_addr  = bus2_fifo_data[81:72];
		bus2_table_wren  = bus2_fifo_data[82];
		bus2_table_data  = bus2_fifo_data[71:0];
	end
	else begin
	    bus2_table_addr  = 10'd0;
		bus2_table_wren  = 1'd0;
		bus2_table_data  = 72'd0;
	end
end
//总线3查找
always @(*)
begin
	if(looking1 || initing) begin
	    bus3_table_addr  = look_addr;
		bus3_table_wren  = look_wren;
		bus3_table_data  = look_data;
	end
	else if(/*~looking1*/ look_update) begin//总线3更新、删除
	    bus3_table_addr  = bus3_fifo_data[81:72];
		bus3_table_wren  = bus3_fifo_data[82];
		bus3_table_data  = bus3_fifo_data[71:0];
	end
	else begin
	    bus3_table_addr  = 10'd0;
		bus3_table_wren  = 1'd0;
		bus3_table_data  = 72'd0;
	end
end
//总线4查找
always @(*)
begin
	if(looking1 || initing) begin
	    bus4_table_addr  = look_addr;
		bus4_table_wren  = look_wren;
		bus4_table_data  = look_data;
	end
	else if(/*~looking1*/ look_update) begin//总线4更新、删除
	    bus4_table_addr  = bus4_fifo_data[81:72];
		bus4_table_wren  = bus4_fifo_data[82];
		bus4_table_data  = bus4_fifo_data[71:0];
	end
	else begin
	    bus4_table_addr  = 10'd0;
		bus4_table_wren  = 1'd0;
		bus4_table_data  = 72'd0;
	end
end
//SRAM输出打拍，使能同步打拍
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    looking_ff1 <= 1'b0;
    else 
    looking_ff1 <= looking1;
end
//SRAM输出打拍，使能同步打拍
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    looking_ff2 <= 1'b0;
    else 
    looking_ff2 <= looking_ff1;
end
//接查找表时是输出查找表内容 表二
//bus1 table data
always @(*)
begin
    if(looking_ff2)begin
	    bus1_lookup_q = bus1_table_q;
		q_al_en       = 1'b1;
	end
	else begin
	    bus1_lookup_q = 72'd0;
		q_al_en       = 1'b0;
	end
end
//bus2 table data
always @(*)
begin
    if(looking_ff2)
	    bus2_lookup_q = bus2_table_q;
	else
	    bus2_lookup_q = 72'd0;
end
//bus3 table data
always @(*)
begin
    if(looking_ff2)
	    bus3_lookup_q = bus3_table_q;
	else
	    bus3_lookup_q = 72'd0;
end
//bus4 table data
always @(*)
begin
    if(looking_ff2)
	    bus4_lookup_q = bus4_table_q;
	else
	    bus4_lookup_q = 72'd0;
end

endmodule
